1. Field of the Invention
The present invention relates to circuits for detecting errors in peak signal amplitudes of digital data signals, and in particular, to peak error detection circuits for detecting and identifying valid detected peak signal errors during selected time windows within digital data signals.
2. Description of the Related Art
Recovering data from data signals which have been transmitted over long lengths of cable at high data rates requires that such data signals be equalized in order to compensate for the signal loss and phase dispersion characteristics of the cable. Further, in those applications where the cable length may vary, such equalization must be capable of adapting according to the length of the cable. Conventional adaptive equalization is typically accomplished through the use of a feedback control signal having an amplitude which is proportional to the pulse height of the equalized data signal. However, such a technique for controlling the adaptive equalization process is very sensitive to amplitude errors in the incoming data signal. Accordingly, it would be desirable to have a peak error detector which, by detecting and identifying valid detected errors in the signal peaks of the incoming data signal, can be used to help generate more consistent and more accurate control over the adaptive equalization process.